The present invention relates to a manufacturing technology of a semiconductor device, particularly, a technology effective when applied to the manufacture of a trench-type element isolation portion formed in the main surface of a semiconductor substrate.
With miniaturization of semiconductor elements to be used for LSI (large scale integration), miniaturization of element isolation portions for electrically isolating semiconductor elements from each other is progressing. In recent years, a shallow trench isolation process has been used widely for LSI, because it is expected to achieve higher integration and higher isolation capacity than a LOCOS (local oxidation of silicon) process.
In the shallow element isolation process, it is the common practice to form an element isolation trench in a predetermined region of a semiconductor substrate and then fill this trench with an oxide film deposited using CVD (chemical vapor deposition). As the trench width becomes narrower, however, the oxide film forms an overhang, which may lead to the formation of a void in the trench. Using an oxide film formed by the method of application which does not form an overhang and can fill the trench completely is therefore under investigation.
For example, Japanese Patent No. 4331133 (Patent Document 1) discloses a technology of applying a solution of perhydropolysilazane having a polystyrene-reduced weight average molecular weight within a range of from 3000 to 20000 to a base material having at least one trench, drying the solution to fill the trench with perhydropolysilzane, and then heating the perhydropolysilazane in a water vapor containing atmosphere to convert it into a siliceous material.
Japanese Patent Laid-Open No. 2006-196843 (Patent Document 2) discloses a technology of forming, in a silicon substrate, a first element isolation trench having a narrow opening width and a second element isolation trench having a wide opening width, filling the first element isolation trench with an HTO (high temperature oxide) film and a polysilazane film, and filling the second element isolation trench with an HTO film, a polysilazane film, and an HDP (high density plasma) film with the proviso that the polysilazane film is not abundantly filled in the second element isolation trench.
Further, K. Ota et al., Symp. VLSI Tech. Dig., pp. 138-139 (2005) (Non-patent Document 1) describes a technology of filling a trench with SOD (spin on dielectric) and HDP to relax the stress, which has been caused by HDP, with SOD.    [Patent Document 1] Japanese Patent No. 4331133    [Patent Document 2] Japanese Patent Laid-Open No. 2006-196843    [Non-patent Document 1] K. Ota, T. Yokoyama, H. Kawasaki, M. Morita, T. Kanai, S. Takahashi, T. Sanuki, E. Hasumi, T. Komoguchi, Y. Sogo, Y. Takasu, K. Eda, A. Oishi, K. Kasai, K. Ohno, M. Iwai, M. Saito, F. Matsuoka, N. Nagashima, T. Noguchi, and Y. Okamoto, “Stress Controlled Shallow Trench Isolation Technology to Suppress the Novel Anti-Isotropic Impurity Diffusion for 45 nm-node High-Performance CMOSFETs”, 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 138-139